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A register is live at a location if it can be read along some CFG path starting from the location. Tr)r r4rcr )rnrs rEanalyze_live_regsrEs(  $&   rGct}|Dcic] }|t}} d}t|D]}|j}t |t r|j |j f}n|j}t}|D]}|j||t|jD]} |jAt | tr1| jtk7r|j||j| j|\} } |j| |j| |||k7s|||<d}|s|S3cc}w)a5Calculate block-entry liveness before exception handling is inserted. Unlike get_cfg(), this models an error edge at each operation that can raise. This matters when an assignment later in the same block overwrites a value that the error handler can still read. Returns inserted for a yield are treated as edges to their continuation blocks. TODO: Unlike run_analysis(), this supports edges from the middle of basic blocks, so we reimplement data flow analysis here. Figure out a way to unify this with run_analysis(). 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